1. Field of the Invention
The present invention generally relates to manufacturing methods of semiconductor devices. More specifically, the present invention relates to a manufacturing method of a semiconductor device, the semiconductor device including a wiring board where a semiconductor chip is flip chip connected and underfill resin configured to seal the semiconductor chip and the wiring board.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a related art semiconductor device. In FIG. 1, “J” (hereinafter “gap J”) indicates a gap between a semiconductor chip 202 and a wiring board main body 211.
As shown in FIG. 1, a related art semiconductor device 200 includes a wiring board 201, the semiconductor chip 202, and underfill resin 203. The wiring board 201 includes the board main body 211 pads 212, solders 213, and a solder resist layer 214.
The board main body 211 includes plural stacked insulation layers (not shown in FIG. 1), wiring patterns (not shown in FIG. 1), and outside connection pads (not shown in FIG. 1). The wiring patterns are provided in plural insulation layers and electrically connected to the pads 212. The outside connection pads are provided on a rear surface 211B of the board main body 211 and configured to be electrically connected to the wiring patterns.
The pads 212 are provided on a front surface 211A of the board main body 211. The semiconductor chip 202 is flip chip connected to the pads 212.
The solders 213 are provided on upper surfaces 212A of the pads 212. The solders 213 are configured to fix bumps 204 on the pads 212. The bumps 204 are connected to electrodes pads 216 of the semiconductor chip 202.
The solder resist layer 214 is provided on the front surface 211A of the board main body 211 so as to surround an area where the pads 212 are formed. The semiconductor chip 202 includes the electrode pads 216. The bumps 204 are provided on the electrode pads 216. The semiconductor chip 202 is flip chip connected to the pads 212 so as to be electrically connected to the wiring board 201 via the bumps 204.
FIG. 2 through FIG. 5 show a manufacturing process of the related art semiconductor device. In FIG. 2 through FIG. 5, parts that are the same as the parts of the related art semiconductor device 200 shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.
A manufacturing method of the related art semiconductor device 200 is discussed with reference to FIG. 2 through FIG. 5. First, in a step shown in FIG. 2, the wiring board 201 is formed by a known method. Next, in a step shown in FIG. 3, the semiconductor chip 202 is flip chip connected on the pads 212 where the solders 213 are formed.
After that, in a step shown in FIG. 4, liquid state underfill resin 221 supplied from a dispenser 219 is led into a gap between the semiconductor chip 202 and the wiring board 201 by capillarity. As a result of this, the liquid state underfill resin 221 is formed between the semiconductor chip 202 and the wiring board 201.
Next, in a step shown in FIG. 5, the liquid state underfill resin 221 shown in FIG. 4 is cured so that the underfill resin 203 is formed between the semiconductor chip 202 and the wiring board 201. As a result of this, the related art semiconductor device 200 is formed.
In the above-discussed manufacturing method of the semiconductor device 200, a case is explained where the liquid state underfill resin 221 is formed between the semiconductor chip 202 and the wiring board 201 after the semiconductor chip 202 is flip chip connected. However, as shown in FIG. 6 and FIG. 7, the liquid state underfill resin 221 may be formed on the wiring board 201 before the semiconductor chip 202 is flip chip connected on the pads 212.
FIG. 6 and FIG. 7 are views showing another manufacturing process of the related art semiconductor device. In FIG. 6 and FIG. 7, parts that are the same as the parts of the related art semiconductor device 200 shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.
Another manufacturing method of the related art semiconductor device 200 is discussed with reference to FIG. 6 and FIG. 7. First, in a step shown in FIG. 6, the liquid state underfill resin 221 is applied on the above-discussed wiring board 201 shown in FIG. 2. Next, in a step shown in FIG. 7, the semiconductor chip 202 is pushed onto the liquid state underfill resin 221 so that the semiconductor chip 202 is flip chip connected to the pads 212. After that, by performing the same step as that shown in FIG. 5, the related art semiconductor device 200 is manufactured. See, for example, Japanese Laid-Open Patent Application Publication No. 2002-121358.
FIG. 8 is a view for explaining problems of the manufacturing process of the related art semiconductor device. FIG. 9 is a view for explaining problems of another manufacturing process of the related art semiconductor device. In FIG. 8 and FIG. 9, parts that are the same as the parts of the related art semiconductor device 200 shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.
In the manufacturing method of the related art semiconductor device 200 (see FIG. 2 through FIG. 5), for example, when a gap J between the semiconductor chip 202 and the board main body 211 is narrow (for example, when the gap J is equal to or less than 35 μm) or when the size of the semiconductor chip 202 is large (for example, a length of one side of the semiconductor chip 202 is equal to or greater than 10 mm), a void 224 shown in FIG. 8 may be formed in the underfill resin 203 due to a short shot of the liquid state underfill resin 221. As a result of this, reliability of electric connections between the semiconductor chip 202 and the wiring board 201 is degraded so that the yield of manufacturing the semiconductor device 200 may be decreased.
In addition, in another manufacturing method of the related art semiconductor device 200 (see FIG. 9), air bubbles may be formed inside the liquid state underfill resin 221 in the step of applying the liquid state underfill resin 221 or the step of flip chip connecting the semiconductor chip 202 by pushing the semiconductor chip 202 onto the liquid state underfill resin 221. As a result of this, voids 225 or 226 shown in FIG. 9 may be formed in the underfill resin 203 and thereby the yield of manufacturing the semiconductor device 200 may be decreased.